A study of value speculative execution and misspeculation recovery in superscalar microprocessors

Recent research has shown that value prediction is a promising way to collapse the true data dependencies. To fully exploit the potential of value speculation, however, a highly accurate value predictor and efficient architectural support for value speculative execution are both necessary. In this paper, we address in detail value speculative execution in a generalized superscalar model based on MIPS R10000. In particular, in order to minimize misprediction recovery penalties, the selective reissuing mechanism is discussed and the necessary support at each pipeline stage are described. In this study, three important design issues are highlighted including: 1) when to resolve/verify the prediction; 2) where to keep the dispatched instructions after they are issued speculatively to enable reissuing; 3) how to dynamically construct the data dependence chain. The critical paths in the possible implementation are also identified. Then, potential benefits on the performance are discussed with different reissue latencies and value misprediction rates. Our experimental results show that there is a great speedup potential, on average up to 12% in our 4-way issue superscalar model, once highly accurate value predictors are available, and also it is shown that value speculation can achieve much higher speedups with better branch predictors and wider issue bandwidth.